With AMD’s upcoming “Zen” architecture we will see a major change in the way AMD designs its CPU cores. It will change from the module core design that was introduced with “Bulldozer”. With this design two cores shared resources of a multi-core processor. The new “Zen” architecture will have dedicated resources the way we saw it before “Bulldozer” and only the last-level cache (L3) will be shared between cores. “Zen” will also implement SMT, much in the same way Intel processors do with HyperThreading.
We will see the first implementation of “Zen” on a very powerful APU that will feature 16 physical “Zen” cores, 32 logical CPUs enabled with SMT, 512 KB of dedicated L2 cache per core and 32 MB of L3 cache. We will also see AMD do some string cleaning of the CPU’s ISA instruction set, removing underused instruction sets and introducing new ones. Other features of this new APU will be a quad-channel DDR4 integrated memory controller, a separate high-bandwidth memory controller dedicated to the integrated graphics with up to 512 GB/s bandwidth, and integrated graphics core featuring “Greenland-class” stream processors.