We have not heard a whole lot about AMD’s Zen architecture in a while. We do know that it will have a 40% IPC increase over the Excavator core. New details tell us that the Zen CPU micro-architecture will focus on significantly increasing the per-core performance, and more particularly the per-core number crunching performance.
In the past AMD’s approach to CPU cores involved modules, which had two physical cores. These cores had a combination of dedicated and shared resources between them. The whole idea was to take Intel’s Core 2 idea of combining two cores into an invisible unit and expand on it.
Well AMD’s implementation of this did not work out the way they intended. Software would sequentially load cores into a multi-module processor, which resulted in a less than optimal scenario than if a one core per module was loaded first and then loaded additional cores across modules. The workaround that AMD came up with would trick software into thinking that a module was actually a core with two threads. So for example an eight core FX-8350 would actually be seen by the software as a 4-core processor with 8 threads.
The approach that AMD is taking with Zen is that they are doing away with the barriers that separated the two cores within a module. It is not one big monolithic core with 4 decoders (which tell the core what to do), 4 ALUs, and four 128-bit wide floating-point units, all in two 256-bit FMACs. This new approach will nearly double the per-core number crunching power. AMD is also implementing SMT technology, which is much like Intel’s HyperThreading.