Thanks to Moore’s Law is Dead’s Tom, we have some information on the future of the EPYC implementation of the Zen6 architecture. AMD hasn’t made clear yet if it plans to keep on using the Zen name for its future architecture. The information has been checked for error and so far, it is claimed that it remains authentic. However, what AMD does in the future remains a question mark and there is a possibility that it might revert its plans.
AMD’s 3rd Gen EPYC update has also been released. The update comes with 3D V-Cache as we have already been informed. Interestingly, the EPYC series we have been talking about earlier will make its debut three generations later. This series has been codenamed ‘Venice’ and will feature the Zen6 architecture. Taking this into consideration, we might see Venice sometime around 2024.
The video highlights some features of the EPYC Venice some of which include the completely new redesigned L2/L3 caches and its heavy reliance on the HBM implementations. By the time Venice is being released, AMD will most likely resort to some other latest technology such as the use of the 3D die. We will be in for quite an interesting combination of the large L3 caches working alongside the HBM memory.
As far as the specs are concerned, there isn’t much to our knowledge about the Zen6 except that it might use a new socket and will come with support for faster DDR5 memory variants. Comparatively, this might go even faster than Turin.