The Xeon Phi Coprocessor family unit took a step into the limelight after the launch of the Tianhe-2 Supercomputer, which attached Intel’s Xeon Processors with the Xeon Phi Coprocessors to exceptional success. Unnecessary to say the landscape of supercomputing might be in for a change. Most Supercomputing collaborate to use HPC (High Performance Computing) GPGPUS (General Purpose GPUs) such as NVIDIA Tesla along with processors, but one of the main disadvantage of the GPGPUS is that they require a special code and a CPU to perform. While on the other hand, the Xeon Phi coprocessor neither demands a special code nor a CPU to work and carry supreme performance.
Knight corner which is a codename for current generation Intel’s Core processor series is made from a 22nm and delivers a peak double precision performance of 1.2 teraflops per coprocessor. Knights Corner Coprocessors uses the latest incorporated Haswell AVX2 instruction set which broadens the Integer register to 256 bit. AVX is the instruction set for floating point operations. Despite the fact that the Knights Corner family uses the 3D Trigate transistors( its power is still unrecognized).
The Knights Landing series of Xeon Phi Coprocessors which will be build with a 14nm process resulting from Skylake and Broadwell and will utilize a much extended 512 bit AVX instruction set. Intel also makes sure of the fact that the Knights Landing Coprocessors will split the 3 Teraflop Barrier in Double Precision performance. Therefore it’s all right to presume that the Xeon Phi Coprocessors of the Knights Landing period will finally make use of the 3D Tri-gate technology.
If in the years to come, the GPGPU is not able to free itself from the fact that it requires a special code and secondly its reliance on the CPU, the future will surely be in the hands of Coprocessors such as the Xeon Phi.
Source: WCCFTech | News Archive