Intel has made a lot of enterprise-released product announcements this week, one of the most interesting is the announcement of their new 56-core Xeon Scalable “Cascade Lake” processor. This is Intel’s first response to AMD’s upcoming 64-core 7 mm EPYC “Rome” processor. Intel’s 56-core processors is an MCM of two 28-core dies, each with a 6-channel DDR4 memory interface. Each of the two cores are built on the existing 14 nm++ silicon and the IPC of each of the 56 cores are unchanged since “Skylake”, but Intel has added several HPC and AI-relevant instruction sets.
Unlike previous models of Xeon Scalable the first “Cascade Lake” Xeon Scalable processor, the Xeon Platinum 9200 is a FC-BGA package and is not socketed. It is a 5903-pin BGA package that uses a common integrated heatspreader with the two 28-core dies underneath. The two dies can communicate with each other over a UPI x20 interconnect link on-package, while each die puts out its second UPI x20 link as the package’s two x20 links, to scale up to two packages on a single board (112 cores).